151376
A NOR gate and a NAND gate are connected as shown in the figure. Two different sets of inputs are given to this setup. In the first case, the inputs to the gates are \(\mathbf{A}=0, \mathrm{~B}=0, \mathrm{C}=0\). In the second case, the inputs are \(A=1, B=0\), \(C=1\). The output \(D\) in the first case and second case respectively are
151376
A NOR gate and a NAND gate are connected as shown in the figure. Two different sets of inputs are given to this setup. In the first case, the inputs to the gates are \(\mathbf{A}=0, \mathrm{~B}=0, \mathrm{C}=0\). In the second case, the inputs are \(A=1, B=0\), \(C=1\). The output \(D\) in the first case and second case respectively are
151376
A NOR gate and a NAND gate are connected as shown in the figure. Two different sets of inputs are given to this setup. In the first case, the inputs to the gates are \(\mathbf{A}=0, \mathrm{~B}=0, \mathrm{C}=0\). In the second case, the inputs are \(A=1, B=0\), \(C=1\). The output \(D\) in the first case and second case respectively are
151376
A NOR gate and a NAND gate are connected as shown in the figure. Two different sets of inputs are given to this setup. In the first case, the inputs to the gates are \(\mathbf{A}=0, \mathrm{~B}=0, \mathrm{C}=0\). In the second case, the inputs are \(A=1, B=0\), \(C=1\). The output \(D\) in the first case and second case respectively are
151376
A NOR gate and a NAND gate are connected as shown in the figure. Two different sets of inputs are given to this setup. In the first case, the inputs to the gates are \(\mathbf{A}=0, \mathrm{~B}=0, \mathrm{C}=0\). In the second case, the inputs are \(A=1, B=0\), \(C=1\). The output \(D\) in the first case and second case respectively are