Semiconductor Electronics Material Devices and Simple Circuits
151253
The expression \(\overline{\mathbf{A}}(\mathbf{A}+\mathbf{B})+(\mathbf{B}+\mathbf{A} \mathbf{A})(\mathbf{A}+\overline{\mathbf{B}})\) simplifies to
1 \(\mathrm{A}+\mathrm{B}\)
2 \(\mathrm{AB}\)
3 \(\overline{\mathrm{A}+\mathrm{B}}\)
4 \(\overline{\mathrm{A}}+\overline{\mathrm{B}}\)
Explanation:
B Let, \(\mathrm{y}=\overline{\mathrm{A}}(\mathrm{A}+\mathrm{B})+(\mathrm{B}+\mathrm{AA})(\mathrm{A}+\overline{\mathrm{B}})\) \(\mathrm{y}=\overline{\mathrm{A}} \mathrm{A}+\overline{\mathrm{A}} \mathrm{B}+(\mathrm{B}+\mathrm{A})(\mathrm{A}+\overline{\mathrm{B}}) \quad[\therefore \mathrm{XX}=\mathrm{X}]\) \(y=\bar{A} B+A B+B \bar{B}+A A+A \bar{B} {[\because X \bar{X}=0]}\) \(y=B(A+\bar{A})+0+A+A \bar{B} {[A+\bar{A}=1]}\) \(y=B(1)+A(1+\bar{B})\) \(y=B+A \) \(y=A+B\)
WB JEE 2022
Semiconductor Electronics Material Devices and Simple Circuits
151255
Two diodes are connected in the following fashion. Provision is made to connect either \(+5 \mathrm{~V}\) or ground \((0 \mathrm{~V})\) to the points \mathrm{A} to \mathrm{B}. The output \(Q\) will act as
1 OR gate
2 AND gate
3 XOR gate
4 NAND gate
Explanation:
B From the circuit diagram when both or either terminal of A and B are at low \((0 \mathrm{~V})\). Then \(5 \mathrm{~V}\) of supply from input appears across resistor \(\mathrm{R}\) in opposite sense of voltage \(V_2\) which is eliminated the voltage across \(\mathrm{R}\). Therefore the final voltage across \(\mathrm{R}\) is zero. But when both terminals of A and B at \(5 \mathrm{~V}\) (high) then both diodes become in reverse bias. Hence no voltage appears across R. So this situation is obtained only in AND gate therefore output Q will be act as AND Gate.
TS- EAMCET-04.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151256
The logic circuit below has the truth table, same as that of
1 NOR gate
2 NAND gate
3 AND gate
4 OR gate
Explanation:
B Given that, The truth table for the given logic circuit is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A}& \mathrm{B}& \mathrm{X}& \mathrm{Y} \\ \hline 0 & 0& 0 & 1 \\ \hline 0 & 1 & 0 & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 1 & 0 \\ \hline \end{array}\) The truth table of the logic circuit same as that of NAND gate.
TS- EAMCET-03.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151257
The logic operation performed by the following circuit is
1 NOR
2 AND
3 NAND
4 OR
Explanation:
B Given that, Truth table for given gate combination is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A} & \mathrm{B}& \mathrm{X} &\mathrm{Y} \\ \hline 0 & 0 & 1 & 0 \\ \hline 1 & 0 & 1 & 0 \\ \hline 0 & 1 & 1 & 0 \\ \hline 1 & 1 & 0 & 1 \\ \hline \end{array}\) So, net output of truth table represent an AND gate.
Semiconductor Electronics Material Devices and Simple Circuits
151253
The expression \(\overline{\mathbf{A}}(\mathbf{A}+\mathbf{B})+(\mathbf{B}+\mathbf{A} \mathbf{A})(\mathbf{A}+\overline{\mathbf{B}})\) simplifies to
1 \(\mathrm{A}+\mathrm{B}\)
2 \(\mathrm{AB}\)
3 \(\overline{\mathrm{A}+\mathrm{B}}\)
4 \(\overline{\mathrm{A}}+\overline{\mathrm{B}}\)
Explanation:
B Let, \(\mathrm{y}=\overline{\mathrm{A}}(\mathrm{A}+\mathrm{B})+(\mathrm{B}+\mathrm{AA})(\mathrm{A}+\overline{\mathrm{B}})\) \(\mathrm{y}=\overline{\mathrm{A}} \mathrm{A}+\overline{\mathrm{A}} \mathrm{B}+(\mathrm{B}+\mathrm{A})(\mathrm{A}+\overline{\mathrm{B}}) \quad[\therefore \mathrm{XX}=\mathrm{X}]\) \(y=\bar{A} B+A B+B \bar{B}+A A+A \bar{B} {[\because X \bar{X}=0]}\) \(y=B(A+\bar{A})+0+A+A \bar{B} {[A+\bar{A}=1]}\) \(y=B(1)+A(1+\bar{B})\) \(y=B+A \) \(y=A+B\)
WB JEE 2022
Semiconductor Electronics Material Devices and Simple Circuits
151255
Two diodes are connected in the following fashion. Provision is made to connect either \(+5 \mathrm{~V}\) or ground \((0 \mathrm{~V})\) to the points \mathrm{A} to \mathrm{B}. The output \(Q\) will act as
1 OR gate
2 AND gate
3 XOR gate
4 NAND gate
Explanation:
B From the circuit diagram when both or either terminal of A and B are at low \((0 \mathrm{~V})\). Then \(5 \mathrm{~V}\) of supply from input appears across resistor \(\mathrm{R}\) in opposite sense of voltage \(V_2\) which is eliminated the voltage across \(\mathrm{R}\). Therefore the final voltage across \(\mathrm{R}\) is zero. But when both terminals of A and B at \(5 \mathrm{~V}\) (high) then both diodes become in reverse bias. Hence no voltage appears across R. So this situation is obtained only in AND gate therefore output Q will be act as AND Gate.
TS- EAMCET-04.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151256
The logic circuit below has the truth table, same as that of
1 NOR gate
2 NAND gate
3 AND gate
4 OR gate
Explanation:
B Given that, The truth table for the given logic circuit is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A}& \mathrm{B}& \mathrm{X}& \mathrm{Y} \\ \hline 0 & 0& 0 & 1 \\ \hline 0 & 1 & 0 & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 1 & 0 \\ \hline \end{array}\) The truth table of the logic circuit same as that of NAND gate.
TS- EAMCET-03.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151257
The logic operation performed by the following circuit is
1 NOR
2 AND
3 NAND
4 OR
Explanation:
B Given that, Truth table for given gate combination is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A} & \mathrm{B}& \mathrm{X} &\mathrm{Y} \\ \hline 0 & 0 & 1 & 0 \\ \hline 1 & 0 & 1 & 0 \\ \hline 0 & 1 & 1 & 0 \\ \hline 1 & 1 & 0 & 1 \\ \hline \end{array}\) So, net output of truth table represent an AND gate.
Semiconductor Electronics Material Devices and Simple Circuits
151253
The expression \(\overline{\mathbf{A}}(\mathbf{A}+\mathbf{B})+(\mathbf{B}+\mathbf{A} \mathbf{A})(\mathbf{A}+\overline{\mathbf{B}})\) simplifies to
1 \(\mathrm{A}+\mathrm{B}\)
2 \(\mathrm{AB}\)
3 \(\overline{\mathrm{A}+\mathrm{B}}\)
4 \(\overline{\mathrm{A}}+\overline{\mathrm{B}}\)
Explanation:
B Let, \(\mathrm{y}=\overline{\mathrm{A}}(\mathrm{A}+\mathrm{B})+(\mathrm{B}+\mathrm{AA})(\mathrm{A}+\overline{\mathrm{B}})\) \(\mathrm{y}=\overline{\mathrm{A}} \mathrm{A}+\overline{\mathrm{A}} \mathrm{B}+(\mathrm{B}+\mathrm{A})(\mathrm{A}+\overline{\mathrm{B}}) \quad[\therefore \mathrm{XX}=\mathrm{X}]\) \(y=\bar{A} B+A B+B \bar{B}+A A+A \bar{B} {[\because X \bar{X}=0]}\) \(y=B(A+\bar{A})+0+A+A \bar{B} {[A+\bar{A}=1]}\) \(y=B(1)+A(1+\bar{B})\) \(y=B+A \) \(y=A+B\)
WB JEE 2022
Semiconductor Electronics Material Devices and Simple Circuits
151255
Two diodes are connected in the following fashion. Provision is made to connect either \(+5 \mathrm{~V}\) or ground \((0 \mathrm{~V})\) to the points \mathrm{A} to \mathrm{B}. The output \(Q\) will act as
1 OR gate
2 AND gate
3 XOR gate
4 NAND gate
Explanation:
B From the circuit diagram when both or either terminal of A and B are at low \((0 \mathrm{~V})\). Then \(5 \mathrm{~V}\) of supply from input appears across resistor \(\mathrm{R}\) in opposite sense of voltage \(V_2\) which is eliminated the voltage across \(\mathrm{R}\). Therefore the final voltage across \(\mathrm{R}\) is zero. But when both terminals of A and B at \(5 \mathrm{~V}\) (high) then both diodes become in reverse bias. Hence no voltage appears across R. So this situation is obtained only in AND gate therefore output Q will be act as AND Gate.
TS- EAMCET-04.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151256
The logic circuit below has the truth table, same as that of
1 NOR gate
2 NAND gate
3 AND gate
4 OR gate
Explanation:
B Given that, The truth table for the given logic circuit is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A}& \mathrm{B}& \mathrm{X}& \mathrm{Y} \\ \hline 0 & 0& 0 & 1 \\ \hline 0 & 1 & 0 & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 1 & 0 \\ \hline \end{array}\) The truth table of the logic circuit same as that of NAND gate.
TS- EAMCET-03.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151257
The logic operation performed by the following circuit is
1 NOR
2 AND
3 NAND
4 OR
Explanation:
B Given that, Truth table for given gate combination is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A} & \mathrm{B}& \mathrm{X} &\mathrm{Y} \\ \hline 0 & 0 & 1 & 0 \\ \hline 1 & 0 & 1 & 0 \\ \hline 0 & 1 & 1 & 0 \\ \hline 1 & 1 & 0 & 1 \\ \hline \end{array}\) So, net output of truth table represent an AND gate.
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Semiconductor Electronics Material Devices and Simple Circuits
151253
The expression \(\overline{\mathbf{A}}(\mathbf{A}+\mathbf{B})+(\mathbf{B}+\mathbf{A} \mathbf{A})(\mathbf{A}+\overline{\mathbf{B}})\) simplifies to
1 \(\mathrm{A}+\mathrm{B}\)
2 \(\mathrm{AB}\)
3 \(\overline{\mathrm{A}+\mathrm{B}}\)
4 \(\overline{\mathrm{A}}+\overline{\mathrm{B}}\)
Explanation:
B Let, \(\mathrm{y}=\overline{\mathrm{A}}(\mathrm{A}+\mathrm{B})+(\mathrm{B}+\mathrm{AA})(\mathrm{A}+\overline{\mathrm{B}})\) \(\mathrm{y}=\overline{\mathrm{A}} \mathrm{A}+\overline{\mathrm{A}} \mathrm{B}+(\mathrm{B}+\mathrm{A})(\mathrm{A}+\overline{\mathrm{B}}) \quad[\therefore \mathrm{XX}=\mathrm{X}]\) \(y=\bar{A} B+A B+B \bar{B}+A A+A \bar{B} {[\because X \bar{X}=0]}\) \(y=B(A+\bar{A})+0+A+A \bar{B} {[A+\bar{A}=1]}\) \(y=B(1)+A(1+\bar{B})\) \(y=B+A \) \(y=A+B\)
WB JEE 2022
Semiconductor Electronics Material Devices and Simple Circuits
151255
Two diodes are connected in the following fashion. Provision is made to connect either \(+5 \mathrm{~V}\) or ground \((0 \mathrm{~V})\) to the points \mathrm{A} to \mathrm{B}. The output \(Q\) will act as
1 OR gate
2 AND gate
3 XOR gate
4 NAND gate
Explanation:
B From the circuit diagram when both or either terminal of A and B are at low \((0 \mathrm{~V})\). Then \(5 \mathrm{~V}\) of supply from input appears across resistor \(\mathrm{R}\) in opposite sense of voltage \(V_2\) which is eliminated the voltage across \(\mathrm{R}\). Therefore the final voltage across \(\mathrm{R}\) is zero. But when both terminals of A and B at \(5 \mathrm{~V}\) (high) then both diodes become in reverse bias. Hence no voltage appears across R. So this situation is obtained only in AND gate therefore output Q will be act as AND Gate.
TS- EAMCET-04.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151256
The logic circuit below has the truth table, same as that of
1 NOR gate
2 NAND gate
3 AND gate
4 OR gate
Explanation:
B Given that, The truth table for the given logic circuit is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A}& \mathrm{B}& \mathrm{X}& \mathrm{Y} \\ \hline 0 & 0& 0 & 1 \\ \hline 0 & 1 & 0 & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 1 & 0 \\ \hline \end{array}\) The truth table of the logic circuit same as that of NAND gate.
TS- EAMCET-03.05.2019
Semiconductor Electronics Material Devices and Simple Circuits
151257
The logic operation performed by the following circuit is
1 NOR
2 AND
3 NAND
4 OR
Explanation:
B Given that, Truth table for given gate combination is, \(\begin{array}{|c|c|c|c|} \hline \mathrm{A} & \mathrm{B}& \mathrm{X} &\mathrm{Y} \\ \hline 0 & 0 & 1 & 0 \\ \hline 1 & 0 & 1 & 0 \\ \hline 0 & 1 & 1 & 0 \\ \hline 1 & 1 & 0 & 1 \\ \hline \end{array}\) So, net output of truth table represent an AND gate.
